The present invention generally relates to transistor gate dielectrics and methods of fabricating the same. More particularly, the invention relates to processes and structures for improving tunnel oxide quality in erasable programmable read-only memories (EEPROMs).
Memory devices such as erasable programmable read-only memories (EPROMs), electrically erasable programmable read-only memories (EEPROMs), or flash erasable programmable read-only memories (FEPROMs) are erasable and reusable memory cells which are often used in digital cellular phones, digital cameras, LAN switches, cards for notebook computers, etc. A memory cell operates by storing electric charge (representing an xe2x80x9conxe2x80x9d state) on an electrically isolated floating gate, which is incorporated into a transistor. This stored charge affects the behavior of the transistor, thereby providing a way to read the memory element. It is therefore crucial that the memory cell be able to maintain the stored charge over time, so that charge leakage does not cause data errors by converting xe2x80x9conxe2x80x9d states to xe2x80x9coff.xe2x80x9d
A flash memory cell typically consists of a transistor, a floating gate, and a control gate above the floating gate in a stacked gate structure. The floating gate, typically composed of polycrystalline silicon (i.e., xe2x80x9cpolysiliconxe2x80x9d), is electrically isolated from the underlying semiconductor substrate by a thin dielectric layer, which is typically formed of an insulating oxide, and more particularly, silicon oxide. Because charge is transferred across the dielectric layer by quantum-mechanical tunneling, this dielectric layer is often referred to as a xe2x80x9ctunnel oxidexe2x80x9d layer. Such tunnel oxide layers are typically approximately 100 xc3x85 thick. Properties of the tunnel oxide must be strictly controlled to ensure the ability to read and write by tunneling, while avoiding data loss through charge trapping or leakage. The control gate is positioned above the floating gate, and is electrically isolated from the floating gate by a storage dielectric layer, such as oxide-nitride-oxide (ONO). Electrical access to the floating gate is therefore only through capacitors.
Storing charge on the floating gate programs a memory cell. This is achieved via hot-electron injection by applying a high positive voltage (approximately 12 V) to the control gate, and a high drain-to-source bias voltage (approximately 6 V). An inversion region is created between the source and drain by the control gate voltage, and electrons are accelerated from the source to the drain by the drain bias voltage. Some fraction of these electrons will have sufficient energy to surmount the tunnel oxide barrier height and reach the floating gate. The floating gate is therefore programmed by collecting and storing these electrons to represent an xe2x80x9conxe2x80x9d state.
An EPROM device can be erased (i.e., returned to an xe2x80x9coffxe2x80x9d state) by exposing the floating gate to ultraviolet light, which excites the stored electrons out of the floating gate. The erasure of an EEPROM or FEPROM cell is accomplished via Fowler-Nordheim tunneling, in which an electric field is applied which is sufficient for the stored electrons to traverse the tunnel oxide and enter the substrate, thereby reducing the stored charge in the floating gate. Under this mechanism for discharging the floating gate, a large negative voltage (e.g., xe2x88x9210 V) is applied to the control gate, and a positive voltage (e.g., 5-6 V) is applied to the source while the drain is left floating. Electrons then tunnel from the floating gate through the tunnel oxide, and are accelerated into the source. Because both the programming and erasing of a memory element takes place via charge transfer processes across the tunnel oxide layer, it is important to minimize the density of interface states and other defects in the form of charge traps in this region which would otherwise create a mechanism for charge trapping or leakage through the tunnel oxide.
Once the stacked gate structure has been fabricated and etched to the appropriate dimensions, the stacked gate structure is encapsulated in a liner layer, followed by the formation of an insulating layer, typically composed of thick, planarized borophosphosilicate glass (BPSG). The liner layer between the source/drain regions and the BPSG, often composed of a low pressure chemical vapor deposition (LPCVD) oxide, serves to minimize out-diffusion of contaminants and dopants from the BPSG. Such out-diffusion might otherwise affect the performance of underlying devices.
While processes have been developed to improve gate dielectric quality, as measured by improved data retention in flash memory devices, for example, a finite soft error rate remains. Accordingly a need exists for further improvements in the fabrication of transistor gate dielectrics.
In accordance with one aspect of the present invention, a method is provided for fabricating an integrated circuit. The method includes providing a silicon semiconductor substrate and forming a stacked gate structure comprising an oxide-silicon interface defined by an initial oxide layer directly in contact with a silicon layer. Upon patterning the stacked gate structure to define a gate stack that includes the oxide-silicon interface, a final oxide layer is formed with additional silicon oxide bonds in the region of the oxide-silicon interface. This result is achieved by exposing the patterned gate stack to elevated temperatures and a dilute steam ambient.
In accordance with another aspect of the invention, a method is provided for fabricating an integrated circuit. The method includes providing a semiconductor substrate and forming a transistor gate stack that includes an oxide-silicon interface between an initial oxide layer and an overlying polycrystalline silicon layer. The transistor gate stack is etched to define a gate electrode that includes the oxide-silicon interface. Polycrystalline silicon grain boundaries are then passivated across the oxide-silicon interface by exposing the grain boundaries to OH species.
In accordance with yet another aspect of the invention, a method is provided for fabricating an integrated circuit. The method includes forming a plurality of layers over a semiconductor substrate, including a buried oxide layer having an interface with a silicon source layer. The plurality of layers is etched to expose a surface of the buried oxide layer. Then, OH species diffuse through the surface across the interface with the silicon source layer to grow additional oxide.
In accordance with yet another aspect of the invention, an integrated circuit includes a transistor with a polysilicon layer directly in contact with an oxide layer, forming an oxide-polysilicon interface between these layers. Along the interface, polysilicon grain boundaries include oxide bonds.
In the illustrated embodiments, a stacked gate structure is formed on the surface of a silicon semiconductor substrate, wherein the stacked gate structure comprises an initial tunnel dielectric layer, one or more polysilicon layers, and an initial storage dielectric layer comprising one or more initial oxide layers. After patterning, the stacked gate structure is exposed to elevated temperatures and a dilute steam ambient comprising steam and hydrogen. This dilute steam ambient process yields OH radicals which readily diffuse through the initial oxide and form additional oxide material substantially uniformly along the oxide-silicon interfaces of the stacked gate structure. The oxidation rate is controlled by diluting the steam with carrier and preferably hydrogen-bearing gas, and by keeping the oxidation temperature moderate. As a result, oxidation is slower relative to the lateral diffusion of OH species from the gate sidewalls across the entire interface. The final tunnel dielectric layer thus has a substantially uniform thickness. Most preferably, the oxide thickness of a storage dielectric layer is simultaneously increased.
Advantageously, the exposure of the stacked gate structure to the dilute steam ambient improves the performance of the resulting device structures. First, the number of defects, such as oxygen vacancies and dangling bonds, in the region of the final tunnel dielectric layer is reduced by the additional oxide material. Second, consumption of thermal budget can be dramatically reduced due to the relatively low temperatures and time of the dilute steam ambient oxidation in forming a substantial fraction of the final storage dielectric layer. And third, the grain boundaries of polysilicon layers within the stacked gate structure are passivated during the dilute steam oxidation, thereby reducing the effect of the grain boundaries on the erase characteristics of the resulting devices.